1. Field of the Invention
The invention relates to clock management in computer systems, and particularly to the management of clock signals to PCI devices.
2. Background Art
The IBM PC AT computer architecture has become industry standard architecture for personal computers, and is typically built around a CPU such as an 80286, 80386, 80486, or 80586 (Pentium.RTM.) microprocessor all manufactured by Intel Corporation. The CPU is coupled to a host (local) bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-66 MHz). The host bus generally includes 16, 32, or 64 data lines, a plurality of address lines, and various control/status lines.
The typical IBM PC AT-compatible computer also includes a system bus, sometimes referred to as an I/O bus. Such a system bus is used to interface communications between a host CPU and a peripheral device, or communications between peripheral devices and host memory. The system bus is coupled to the host bus via certain interface circuitry. The system bus includes generally 8, 16, or 32 data lines, a plurality of address lines, as well as control/status lines.
One commonly used system bus is the PCI bus. The PCI bus has been developed to establish an industry standard for system bus architectures, particularly those interfacing with high bandwidth functions. The PCI bus is described in detail in "PCI Local Bus Specification", Revision 2.1 (Portland, Oreg., PCI Special Interest Group, 1995), incorporated by reference herein.
The PCI specification, Revision 2.1 (herein referred to as "PCI 2.1") requires that each device on the PCI bus receive its own clock signal. Thus, there can be no clock sharing, and the computer system circuitry must generate multiple PCI clocks. PCI 2.1 further requires that the clock signal to each PCI device be synchronous (or in phase) with each of the clocks generated to each of the other PCI devices. To be considered in phase, PCI 2.1 requires that each clock have no more than a 2 ns skew from all other clocks generated to PCI devices.
Moreover, many system functions require that each PCI clock be in phase (within predefined tolerance limits) with the CPU clock, that is, the CPU clock and each of the PCI clocks must be synchronous. In a synchronous mode of operation, devices sample certain signals on the rising (or falling) edge, of the clock. If clocks are too far out of phase, then sampled signals may be incorrect or sampled at an incorrect time.
Generally, a clock generator will generate both a CPU clock signal and a PCI clock signal. PCI bus interface circuitry will receive the PCI clock signal and buffer it to obtain the multiple PCI clocks required for each device on the PCI bus. Often, however, because of the buffering to obtain multiple PCI clocks, as well as any additional buffering of the CPU clock, obtaining each of these clocks in phase (e.g., within 2 ns) can be difficult.
In addition, PCI 2.1 specifies the implementation of a CLKRUN# signal, which is an optional signal used to stop clock signals to devices, allowing a system to consume less power in certain states of inactivity. When a host or PCI bus controller drives CLKRUN# high, a PCI device still requiring a clock must pull the CLKRUN# signal low within four clock cycles. If no device pulls CLKRUN# low, the host will stop the clocks to all PCI devices. Many PCI devices, however, do not support the optional CLKRUN# signal and require a clock to run at all times.
Also in recent years, and particularly with the growing popularity of notebook computers, efforts have been made to reduce the size and improve the manufacturability of PC AT-compatible computers. Specifically, several manufacturers have developed "chipsets", which integrate a large amount of the system interface circuitry and other circuitry onto only a few chips. Examples of a chipset used in a notebook computer is Viper-N.TM. produced by OPTi, Inc. of Milpitas, Calif. The interface circuitry integrated into chipsets often includes interface circuitry between the host bus and the ISA bus and/or the PCI bus. In efforts to reduce system hardware, as many computer system functions as possible are sought to be incorporated into a chipset.
Therefore, it is desirable to develop a computer system that not only minimizes clock skew in clocks provided to PCI devices, but also fully supports devices that can implement CLKRUN# and those that do not. Further, it is desirable to incorporate those clock management functions along with many other interface functions into a chipset to minimize computer system hardware.